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| TECHNICAL DATA IN74HC74A Dual D Flip-Flop with Set and Reset High-Performance Silicon-Gate CMOS The IN74HC74A is identical in pinout to the LS/ALS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC74AN Plastic IN74HC74AD SOIC TA = -55 to 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs Set L H L PIN 14 =VCC PIN 7 = GND H H H H Reset H L L H H H H L H Clock X X X Data X X X H L X X Outputs Q H L H * Q L H H* L H H L No Change No Change H H X No Change *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. X = don't care 79 IN74HC74A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260 Unit V V V mA mA mA mW C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 80 IN74HC74A DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 2.0 85 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 20 125 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 80 A A V Unit VIH Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 V VIL V VOH V VOL Maximum Low-Level Output Voltage VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA IIN ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VIN=VCC or GND IOUT=0A 81 IN74HC74A AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns) VCC Symbol Parameter V Guaranteed Limit 25 C to -55C 6.0 30 35 100 20 17 105 21 18 75 15 13 10 85C 125C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Flip-Flop) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 - 4.8 24 28 125 25 21 130 26 22 95 19 16 10 4.0 20 24 150 30 26 160 32 27 110 22 19 10 MHz tPLH, tPHL ns tPLH, tPHL ns tTLH, tTHL ns CIN pF Typical @25C,VCC=5.0 V 39 pF CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns) VCC Symbol tsu Parameter Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Set or Reset (Figure 2) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 80 16 14 3.0 3.0 3.0 8.0 8.0 8.0 60 12 10 60 12 10 1000 500 400 Guaranteed Limit 25 C to-55C 85C 100 20 17 3.0 3.0 3.0 8.0 8.0 8.0 75 15 13 75 15 13 1000 500 400 125C 120 24 20 3.0 3.0 3.0 8.0 8.0 8.0 90 18 15 90 18 15 1000 500 400 Unit ns th ns trec ns tw ns tw ns tr, tf ns 82 IN74HC74A Figure 1. Switching Waveform Figure 2. Switching Waveform Figure 3. Switching Waveform Figure 4.Test Circuit EXPANDED LOGIC DIAGRAM 83 |
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